Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, December 2, 12:00-1:00 p.m. HH-1112

 

Wing Chiu Tam
Carnegie Mellon University

Precise Failure Localization using Automated Layout Analysis of Diagnosis Candidates

Diagnosis of integrated circuits (IC) is an indispensable part of IC manufacturing for yield improvement. It is only after the cause of failure (i.e., the “defect”) is precisely located, exposed, and understood can any corrective measure be taken. Test data are used as the starting point for many diagnosis techniques. By analyzing the responses of the failed parts to its input test patterns, much can be learned about the potential locations of the defects. Traditional software-based diagnosis usually identifies several lines where the failure might occur. However, the lines can span across multiple layers and can be very long in length. This makes physical failure analysis (PFA) difficult.

Precise Failure Localization using Automated Layout Analysis of Diagnosis Candidates Diagnosis of integrated circuits (IC) is an indispensable part of IC manufacturing for yield improvement. It is only after the cause of failure (i.e., the “defect”) is precisely located, exposed, and understood can any corrective measure be taken. Test data are used as the starting point for many diagnosis techniques. By analyzing the responses of the failed parts to its input test patterns, much can be learned about the potential locations of the defects. Traditional software-based diagnosis usually identifies several lines where the failure might occur. However, the lines can span across multiple layers and can be very long in length. This makes physical failure analysis (PFA) difficult. In contrast, there are emerging diagnosis techniques that not only give the suspect line but also the logical conditions of the neighboring lines for the suspect line to become faulty. A closer analysis of the diagnosis outcome reveals the role that the neighbors might have in the activation conditions of the defect. In particular, it suggests some neighbors are particularly important in activating the defect while others are not. Combining this information with the physical description of the design (i.e., the layout), one might achieve further localization within a given suspect line. This work describes an approach that automatically analyzes the diagnostic outcome with the layout to improve failure localization to reduce PFA turnaround time. Experimental results show a significant improvement in failure localization when this proposed approach is applied to 106 real IC failures. The accuracy of the proposed approach is validated through a SPICE simulation of circuits with injected failures.

Bio

Wing Chiu Tam has just completed his second year as ECE PhD student in Carnegie Mellon University and he is advised by Prof. Shawn Blanton and Prof. Wojciech P. Maly. His research interest includes defect localization, IC diagnosis and defect modeling.