Jon Proesel Carnegie Mellon University

Flash and Pipeline ADC Designs for Nanoscale Digital CMOS

Clear electrical and economic motivations exist for implementing analog circuits in nanoscale digital CMOS processes. On-chip integration of analog and digital circuits reduces the required I/O power and area and simplifies printed circuit boards. A single-chip solution is cheaper due to the reduction in total silicon area, packaging costs, and board size. However, the electrical and economic benefits can only be obtained if analog circuits achieve high performance and yield in nanoscale digital CMOS.

Analog-to-digital and digital-to-analog converters are the interface between the digital world and the analog world, making these converters essential to modern circuit design. Implementing these converters in nanoscale digital CMOS is key to realizing the electrical and economic benefits described above.

This work focuses on analog-to-digital converter (ADC) design in nanoscale digital CMOS, in particular flash and pipeline ADC architectures and circuits. Inverter-based analog design is discussed, in which the CMOS inverter is used as either a comparator or an amplifier. A 5-bit voltage scaling flash ADC using a resistor-inverter comparator is presented with silicon results. A pipeline ADC using inverter-based amplifiers is described. Random mismatch is addressed by adaptive post-silicon tuning using a successive approximation (SA) architecture. A flash ADC using post-silicon tuning and the SA architecture is proposed as future work.

Bio:

Jon Proesel is a Ph.D. student in the Electrical and Computer Engineering Department at Carnegie Mellon University, where he is advised by Prof. Larry Pileggi. He received his B.S. degree in computer engineering from the University of Illinois at Urbana-Champaign in 2004. His thesis research is focused on analog-to-digital converter design in nanoscale digital CMOS processes, and his research interests include all aspects of analog, mixed signal, and digital circuit design.