Umit Y. Ogras Carnegie Mellon University

Modeling, Analysis and Optimization of Networks-on-Chip Communication Architectures

Traditionally, design space exploration for systems-on-chip (SoC) have focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the design of the communication architecture plays a major role in defining the area, performance and energy consumption figures of the overall system. Furthermore, the global interconnects cause severe on-chip synchronization errors, unpredictable delays and high power consumption. To mitigate these kinds of effects, the network-on-chip (NoC) communication architectures emerged recently as a promising alternative to the classical bus-based and point-to-point communication architectures.

This talk will cover a few fundamental research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, I will first present a mathematical model for on-chip routers and demonstrate its use for NoC performance analysis. Then, I plan to discuss two performance optimization techniques based on topology customization and flow control. Finally, I will present a globally asynchronous-locally synchronous NoC design with multiple voltage-frequency islands and discuss its advantages in terms of energy minimization and clock synchronization.

Bio:

Umit Y. Ogras is a postdoctoral research associate in the Department of Electrical and Computer Engineering, Carnegie Mellon University. He received his Ph.D. degree in Electrical and Computer Engineering from the same department in 2007. His research focuses on communication-centric design methodologies for nanoscale systems-on-chip, with a special interest in network-on-chip communication architectures. He received his M.S. degree from The Ohio State University, and his B.S. from the Middle East Technical University, Turkey, both in electrical engineering.