Carnegie Mellon University
Cost-Effective Lifetime Optimization for NoC-Based MPSoCs
As semiconductor manufacturing processes scale, lifetime
reliability problems are predicted to increase rapidly. Of
particular concern is the exponential growth of wear-out induced
permanent transistor failure, and the resulting failure of
processors, memories, and interconnect in everyday MPSoCs.
Designers will need to respond by addressing the lifetime
of all designs, not simply those intended for safety-critical
or high-availability systems.
The designers of such everyday systems rely on automation
approaches to meet time-to-market constraints, but at present
there are few tools to assist with design lifetime optimization.
We propose meeting this need with a novel synthesis approach
that generates lifetime-enhanced application-specific NoC-based
MPSoCs by finding the custom communication architectures and
redundancy allocations that present the best trade-offs of
cost and lifetime in the presence of permanent component failure.
Given an application and hardware/software partitioning, our
approach will, in a cost-sensitive way, distribute network
bandwidth and redundant resources to enable task remapping
and traffic re-routing in order to increase the probability
that systems are able to continue to operate even after components
To gain insight into how to organize such a tool, we conducted
a design space case study exploring the relationship of system
communication architecture, redundancy allocation, system
cost and system reliability in NoC-based MPSoCs. Based on
this case study, we divide design space exploration into two
iteratively repeated steps: NoC Search and RA Search. NoC
Search uses cause-of-failure analysis to make incremental
changes to the system communication architecture. RA Search
then searches for allocations of redundant capacity to processors
and memories that offer the best reliability and cost trade-offs.
NoC Search and RA Search are repeated a number of times, resulting
in a set of cost-reliability Pareto-optimal design points
for the designer to choose from. This talk focuses on the
experimental support for such a design space exploration formulation,
and presents some initial results from a preliminary implementation
of RA Search.
Brett H. Meyer is a Ph.D candidate advised by Professor Don
Thomas in the Department of Electrical and Computer Engineering
at Carnegie Mellon University. He received his B.S. in electrical
engineering from the University of Wisconsin-Madison in 2003,
and his M.S. in electrical and computer engineering from Carnegie
Mellon University in 2005. His research is presently focused
on the automation of embedded multiprocessor-systems-on-chips
for increased lifetime in the presence of permanent component