Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, April 8, 12:15-1:15 p.m. HH-1112

Mark McCartney
Carnegie Mellon University

Variability-tolerant SRAM Read Path Timing in Deeply Scaled Processes

As processes scale into the nanometer regime, device variability is becoming an increasing concern for static random access memory (SRAM) designers. SRAMs are particularly susceptible to device variability due to the large number of devices that are at or near minimum size in the 6T cell arrays. Read path timing has long been a challenge with cell-to-cell delay variation increasing as transistor sizes scale down. One promising solution lies in SRAM post-silicon tuning techniques which can use random mismatch to combat the effects of variability on power and delay.

The read path in modern designs typically uses either small-swing differential bitlines or large-swing single-ended bitlines. Low-power operation with differential bitline sensing requires a precisely timed sense enable signal that matches worst-case bitline delay across process, voltage and temperature (PVT) variations. Replica bitlines (RBL) were designed to meet this constraint; however, because they use cells very similar to the core 6T SRAM cells, conventional RBLs are also sensitive to intra-die device mismatch.

Margining for this mismatch is not an attractive option, as it will reduce performance and increase power. A promising alternative is post-silicon tuning of the RBL. Researchers have proposed a configurable RBL [1] to overcome device mismatch by selecting the driver cells that result in the best performance while still preserving the similar PVT delay variation of the conventional replica bitline. Interestingly, increasing local mismatch actually improves cRBL performance; it can be considered a rare example of variability-assisted design. A major challenge of this configurable scheme is the methodology to accurately set the configuration while minimizing the impact on manufacturing test.

[1] Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai, and Lawrence T. Pileggi. Variation-tolerant SRAM sense-amp timing using configurable replica bitlines. Submitted to IEEE Custom Integrated Circuits Conference, April 2008.


Mark McCartney earned his B.S. degree in Computer Engineering in 2005 from Case Western Reserve University and joined the ECE department at Carnegie Mellon University in fall 2005, advised by Ken Mai. In 2004 he worked at Intel Corporation on memory box architecture and cache access patterns. His interests include memory design for variability tolerance and error-correcting codes for enhanced yield and soft error resilience.