Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, February 26, 12:15-1:15 p.m. HH-1112


Vikram Iyengar
Vikram Iyengar

At-Speed Structural Test of ASICs

At-speed test of integrated circuits is critical to detect subtle delay defects in integrated circuits. In this talk, I describe IBM's new method for at-speed structural test of ASICs, having no tight restrictions on the
circuit design. I will present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. The talk also describes a method to test asynchronous clock domains simultaneously.


Vikram Iyengar received his MS from Boston University in 1998 and his PhD from Duke University in 2002, both in Computer Engineering. He is with ASICs test methodology at IBM in Pittsburgh, PA. Vikram's research interests are at-speed structural test and path delay test of integrated circuits.