Electrical & Computer Engineering     |     Carnegie Mellon

Part I: Tuesday, November 4, 2008 12:00-1:00 p.m. HH-1112

Part II: Tuesday, November 18, 2008 12:00-1:00 p.m. HH-1112


Eric Chung
Carnegie Mellon University

A Bluespec Tour

Bluespec System Verilog is a new hardware description language that promises dramatic improvements in hardware design productivity. Bluespec offers three key features over conventional HDLs to achieve this: 1) the use of atomic rules (or transactions) to manage complex concurrency, 2) incorporating language features that enable designers to capture their designs at a high level of programming abstraction, and 3) the extensive use of compile-time error-checking to reduce the probability of bugs. In addition, from a high-level source description, the Bluespec compiler is able to generate quality, fully-synthesizable Verilog without compromising on metrics such as area or clock frequency.

Over the course of two seminars, I will present an in-depth practical tutorial to Bluespec. The first part will primarily cover key concepts such as rules, interfaces, basic libraries, and common types. A large number of examples will also be given. The second part will cover more advanced topics such as provisos (for parameterization), multiple-clock domains, and advanced scheduling concepts. Attendees will also receive prepared lab exercises if interested in trying out Bluespec on their own.


Eric just completed his fourth year as a PhD student at Carnegie Mellon University and is advised by Professor James C. Hoe. He is interested in FPGA-accelerated full-system multiprocessor simulation technologies and developing useful instrumentation components to accompany them.