Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, October 9, 12:15-1:15 p.m. HH-1112


Yun Chiu
University of Illinois
at Urbana-Champaign

Harnessing Power and Variability of Analog Circuits in Scaled CMOS

As technology scaling approaches the fundamental physical limit, the inevitable consequences of such scaling on integrated-circuit performance have been the limelight of research and development lately in academia and industry. Since elevated process variations and reduced supply voltages present fundamental challenges to implement high-performance CMOS circuits in deeply scaled process nodes, one cannot help asking: can we keep benefiting from scaling? What comes to rescue the roadmap? In this talk, after identifying a few critical needs of the IC industry, I will examine some fundamental issues associated with the design of analog-digital interface circuits. As more and more realized by the analog community, it appears that system-level techniques increasingly play a key role in implementing critical analog functionalities in future technologies. A few design examples will also be given to showcase, here in the middle of nowhere, the ongoing research activities and the projects we pursue in analog circuit design


Yun Chiu is an Assistant Professor in the ECE Department of the University of Illinois at Urbana-Champaign. Dr. Chiu received his Ph.D. degree in EECS from the University of California at Berkeley. Prior to joining UIUC, he spent two years working in industry between 1997 and 1999. Dr. Chiu was the recipient of many awards from the University of California, the Intel Corp., and the China's Ministry of Education. In 2004, he also received the Jack Kilby Outstanding Paper Award from ISSCC. His past work includes CMOS switched-capacitor circuits and data converters. Recently, his research is mainly focused on investigating the application of adaptive signal-processing techniques to power-efficient, high-performance analog/RF circuits for communication applications.