Soner Yaldiz Carnegie Mellon University

Efficient Statistical Analysis of SRAM Self-Timing Circuits

The aggressive scaling of integrated circuit (IC) technologies has made circuit design extremely difficult. One of the important design challenges stems from the process variations that become increasingly large at 65nm and beyond. Due to the small-size transistors used in SRAM (static random access memory) cells, SRAM circuits are extremely sensitive to both systematic variations and random mismatches. Further exacerbating the problem is the increasing impact of environmental fluctuations, such as those due to temperature and voltage supply variations. For this reason, statistical analysis of process and environmental variations for SRAM circuits has been identified as a top priority for today's memory design problems.

In this talk, I will present a system-level statistical analysis methodology for SRAM self-timing circuits which considers both process variations and environmental fluctuations. This methodology can be used to estimate two important performance metrics: (1) self-timing path delay which is a significant portion of the read delay for high-speed SRAM circuits; and (2) self-timing failure probability which is a critical failure mechanism for read error. The methodology can be used for both early-stage design exploration (i.e., architecture selection and circuit optimization) and parametric yield estimation for the final design.

Bio:

Soner Yaldiz received his B.S. degree in microelectronics from Sabanci University, Turkey in 2004 and M.S. degree in electrical and computer engineering from Koc University, Turkey in 2006. He is currently pursuing a Ph.D. degree in electrical and computer engineering at Carnegie Mellon University and is working under the supervision of Prof. Larry Pileggi. His current research focuses on statistical modeling and design methodologies for manufacturability.