Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, January 23, 12:15-1:15 p.m. HH-1112


Amith Singhee
Carnegie Mellon University

From Finance to Flip Flops: Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis

Problems in computational finance share many of the characteristics that challenge us in statistical circuit analysis: high dimensionality, profound nonlinearity, stringent accuracy requirements, and expensive sample simulation. I will present a detailed experimental study of how one celebrated technique from this domain -- Quasi-Monte Carlo (QMC) analysis -- can be used for fast statistical circuit analysis. In contrast with traditional pseudo-random Monte Carlo sampling, QMC substitutes a (shorter) sequence of deterministically chosen sample points. Across a set of digital and analog circuits, in 90nm and 45nm technologies, varying in size from 30 to 400 devices, we can obtain speedups in parametric yield estimation from 2X to 50X.


Amith Singhee is a PhD student in ECE. He got his B.Tech. from the Indian Institute of Technology, Kharagpur, in 2000, and MS from CMU in 2002.  From 2002-04 he worked at Neolinear, and Cadence Design Systems, as a lead researcher for the NeoCircuit analog synthesis tool. His interests lie in modeling, simulating and optimizing circuits, especially in the presence of random manufacturing variations.