|
Nicola Nicolici
McMaster University
|
Combined Input/Output Test Data Compression for Digital Integrated Circuits
As digital logic is continually being more densely packed into each integrated circuit, gate density outstrips pin density and sophisticated manufacture test technologies are required to cost-effectively screen chips for defects inherent to the semiconductor fabrication process. Scan based testing which provides observability/controllability to the internal state elements of a circuit, coupled with combinational automatic test pattern generation (ATPG), has established itself as a successful solution for testing digital integrated circuits. Introduction of scan however results in large volumes of test data which must be stored on the automatic test equipment (ATE). The increase in ATE memory and tester channel bandwidth, adds to the escalating expenses for test equipment and, consequently, increases the product cost. This problem has been addressed in the form of test data compression that uses hardware placed on-chip, and is comprised of two aspects: 1) input compression which takes advantage of the sparse nature of ATPG patterns, using compressed seeds from the ATE to reproduce the specified bits of test cubes and 2) output compression which compresses the circuit response and delivers a signature back to the tester.
Test data compression has been subject to significant research in the past decade. In this talk we will overview the most relevant approaches and explain their distinguishing features and advantages. We will also discuss the recent work on combined input/output compression developed at McMaster University.
Nicola Nicolici received the Dipl. Ing. degree in computer engineering from the “Politehnica” University of Timisoara, Romania, in 1997, and the Ph.D. degree in electronics and computer science from the University of Southampton, U.K., in 2000. In 2001 he joined McMaster University, Ontario, Canada where currently he is an Associate Professor in the Department of Electrical and Computer Engineering. His research interests are in the area of electronic test automation, with special emphasis on core-based system-on-a-chip test, power-constrained test, test data compression and silicon debug and diagnosis. He was the recipient of the IEEE TTTC Beausang Award for the Best Student Paper at the International Test Conference (ITC 2000) and the Best Paper Award at the IEEE/ACM Design Automation and Test in Europe Conference (DATE 2004).
|
