Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, February 8, 12:15-1:15 p.m. HH-1112


Anne Meixner
Intel Corporation

The Challenges of Testing I/Os on Cheap Testers

Gordon Moore, now Chairman Emeritus of Intel Corporation, predicted in 1965 that the number of transistors on a chip would double every couple of years.  In the 39 years since the introduction of "Moore's Law", there have been two constants:  predictions that the end of Moore's Law is just around the corner, and the semiconductor industry proving those predictions wrong by producing ever smaller transistors.  The convergence of silicon nanotechnology with 300mm manufacturing has created unique challenges and opportunities.  This presentation will review how Intel is approaching the Semiconductor test challenges.

Like the chair you are sitting on, IC's are tested prior to customer shipment.  Testing screens out bad product; be it the obvious- not functioning or subtle- reliability fails.  Today's VLSI products are complex parts composed of 10's of millions of transistors on 65 nanometer CMOS technology. A view of a recent Intel microprocessor layout draws analogies to a small city. The testing of this "small city" is limited to about 300 primary inputs/outputs. The modern microprocessor contains a large SRAM, high speed clocking, complex logic, and higher speed I/O all of which require specialized testing to meet the high quality demands of less than 500 Defects Per Million.  This talk introduces the audience to IC testing terminology, Design for Test (DFT) and basic flows used in a High Volume Manufacturing environment.   Specific challenges to the testing of microprocessor and chipset interface circuitry > 800 MTS will be discussed.  Note, 10 years ago the I/O data rate was at 66 Mega Transfers per Second (MTS). Today, the data rates range from 1033 MTS and 2.5 GTS.  For communication ICs which have low volumes and high profit margins, expensive test solutions are often pursued.  Such test solutions are not feasible for computer IC's, which have volumes in the 10's of millions per year and much lower profit margin.  This talk will review Intel’s use of timing margin to address this challenge and extends to how future high speed IO will be tested.


Anne Meixner works in Assembly Test Technology Development organization within Sort Test Technology Development department at Intel Corp.  Anne has over 20 years of IC test experience, 12 years with Intel at the Ronler Acres campus in Oregon. 

In December 1993, Anne earned her PhD from Carnegie Mellon University in Electrical and Computer Engineering.  For the past 9 years Anne has been involved in the development of I/O test methods.  She has published several Intel technical papers and three International Test Conference (ITC) papers, two of which have been awarded Best paper.  She has served on the Program committee for 6 years.  She has been awarded 3 US patents in the area of Design for Test.

To balance her life at Intel, Anne teaches Alpine skiing from December to April at Mt. Hood and volunteers with her husband, Mike, at their neighborhood farmer's market from May to October.