Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, November 20, 12:15-1:15 p.m. HH-1112


Ron Ho
Carnegie Mellon University

Exploiting capacitance in high-performance computer systems

Over the past several decades, the technology scaling of silicon circuits has completely transformed the power and performance space of VLSI chips. Sun's Niagara2 processor, running at 1.4 GHz, contains eight full compute cores, 4 MB of on-chip cache, and can switch between 64 different threads while consuming under 100 W.

However, continued technology scaling also presents designers with several challenges. Chief among these are the increasing costs of communication. On a chip, scaled metal wires are getting slower and slower, while consuming more and more of a chip's power budget. Off a chip, area solder balls are not scaling nearly as fast as transistors, making chip-to-chip communication a worsening bottleneck, even with the liberal use of high-power serial links on every I/O pad.

In Sun's research labs, we are looking at solutions that reduce these communication costs. We have demonstrated in a number of test chips the feasibility of using capacitive coupling for on-chip wires to reduce both energy (by 10x) and latency (by 1.4x) over traditional repeated wires. We have also shown how using capacitive coupling can dramatically improve the bandwidth density between multiple chips (by more than 10x) and at much lower power (by 10x) over serial links over solder balls.

This talk will cover both capacitive coupling technologies and explore some of the circuit and other design issues that make both solutions interesting.


Ron Ho is a Distinguished Engineer at Sun Microsystems, working in Sun Lab's VLSI Research Group. He received his Ph.D. from Stanford University in 2003, where he studied under Mark Horowitz and examined the scaling effects of long wires. From 1993-2003, he was at Intel Corporation in Santa Clara, CA, where he worked on CPUs such as the Pentium II processor and the 3rd-generation Itanium processor. There he focused on areas such as datapath automation, memory design, CAD for on-chip inductance, clocking, and process monitoring. In 2003, he joined Sun Labs in Menlo Park, CA, where he has been working on chip-to-chip and on-chip communication technologies, memory design, and asynchronous circuits. In 2004 Sun awarded Ron its Chairman's Award for Innovation. Ron is a member of the technical program committees for the IEEE Int'l Solid-State Circuits Conference, the IEEE Hot Interconnects Conference, and the IEEE Symposium on Asynchronous Circuits and Systems; and he will be the General Chair of the 2008 IEEE/LEOS Workshop on Interconnections Within High-Speed Digital Systems.