Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, October 30, 12:15-1:15 p.m. HH-1112


Alyssa Bonnoit
Carnegie Mellon University

Adaptive Bias Control for Variability Tolerance in Back-Gated CMOS Technologies

In accordance with classic scaling theory, transistor density and chip performance have increased at a dramatic rate over the past several decades. These scaling trends are at risk, however, due to mounting problems such as variability and power. Back-gated MOSFETs provide a promising direction for continued scaling. These are fully-depleted SOI devices with a weak back gate shared as a common substrate among groups of devices. Back-gated MOSFETs reduce variability because the channel can be undoped, thus eliminating random dopant fluctuations, and the back gate enables post-process tuning, thus eliminating inter-die and spatial, intra-die variability. Additionally, sub-threshold leakage is reduced due to improved short-channel effects. In order to tune devices with the back gate, a circuit to automatically configure the voltage on the back gates is needed.

Several previous studies proposed digital circuits to adaptively configure the applied body to source voltage on bulk MOSFETs. Tschanz et al. externally set the NFET body bias, and incrementally reduce the voltage on the PFET body bias until the desired speed through a critical path is met [1]. Kang et al. monitor the speed of a chip with the on-chip PLL and the NFET to PFET ratio with an inverter, and then use decoders to determine the body biases [2]. Since the body voltage is an analog signal, these implementations require an analog-to-digital converter, and are therefore inefficient in terms of area and power.

This work presents ongoing work toward an analog circuit to configure the body voltage. Our system uses two inter-locked feedback loops to dynamically configure the NFET and PFET back gate voltages. The first loop compares the input and output of an inverter and then uses a charge pump to adjust the NFET back gate voltage until the input and output of the inverter are equal. The second loop functions like a PLL. It uses a phase-frequency detector to compare the output of a voltage controlled oscillator (VCO) to a reference clock, followed by a charge pump which adds or removes charge from the PFET back gate until clock from the VCO is matched to the reference clock. By using completely analog elements, our proposed control circuit is able to achieve a substantial reduction in area and power over previous implementations.


Alyssa Bonnoit is a PhD candidate advised by Professor Larry Pileggi in the Department of Electrical and Computer Engineering at Carnegie Mellon University. She received her B.S. in electrical engineering from Swarthmore College in 2003, and worked at IBM from 2003 through 2006. Her research is presently focused on variation-aware design of scaled CMOS technologies.