Dong Hun Shin Carnegie Mellon University

A Unified Modeling and Design Methodology for RFICs Using Parameterized Sub-Circuit Cells

The design of RFIC is unduly challenging due to the immense complexity of modeling parasitic effects in circuit components and the lack of a formal design methodology. As future wireless standard moves towards to higher frequencies for more bandwidth, RF circuit tolerance for parasitic is diminishing. At the same time, parasitic effects in scaled devices are becoming more complicated. Moreover, the increasing cost of photolithography mask set makes design re-spins for tuning RF circuit performance no longer an acceptable option as in older generation technologies. To minimize design cost and reach the ultimate goal of first pass silicon success for future generations of RFICs, today's trial and error approach must be replaced by a systematic design and modeling methodology.

Standard cell-based analog design was first proposed and attempted in a 3- m CMOS process nearly two decades ago. The feasibility of such analog design methodology is hampered by the performance penalty, design flexibility and area overhead. Providing fine enough granularities in the standard cells to support a wide range of analog circuit topologies and performance requirements remains a daunting task. On the other hand, RF circuits have two characteristics which make them well suited for cell-based design. First, RF circuit topologies (excluding biasing circuits) are less complex in comparison to traditional analog design as the number of transistors can be utilized is restricted due to the intrinsic device speed limitation. Second, RF circuit behaviors have more pronounced layout dependency owing to their higher sensitivity to device and interconnect parasitic. While the importance of cell-based RF modeling is well known because of the inherent benefit from avoiding model uncertainty associated with full-custom layout, cell-based RF design has not been explored primarily due to the lack of a properly structured cell hierarchy to efficiently support the full range of RF circuit needs. This talk addresses the issue by partitioning RF circuits at the sub-circuit level to enable a unified modeling and design platform for RFICs.

Bio:

Dong Hun Shin received the B.S. and M.S. degrees in Electronics Engineering from Kon-kuk University Seoul, Korea, in 1996 and 1998, respectively. From 1998 to 2004, he was with Ansoft Corporation as an application engineer for high-frequency products including HFSS, Q3D, and Ansoft Designer, focusing on the high-frequency and high speed signal integrity applications. In 2004, he became a graduate student in the Department of Electrical and Computer Engineering at Carnegie Mellon University to pursue his Ph.D. in the field of Radio-Frequency Integrated Circuits design. In the summer of 2005, he has held internship at Marvell Semiconductor in Sunnyvale, CA, where he worked on design of T/R switch for 802.11 applications.