Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, March 28, 12:00-1:00 p.m. HH-1112


Umit Ogras
Carnegie Mellon University

Challenges and Promising Solutions in Networks-on-Chip Design

At nanoscale domain, it becomes possible to integrate large amounts of embedded memory and hundreds of IP cores running multiple concurrent processes on a single chip. The design of complex SoCs faces a number of design challenges. First, the richness of computational resources places tremendous demands on the communication resources. Second, global interconnects cause severe on-chip synchronization errors, unpredictable delays and high power consumption. Finally, increasing costs and tight time-to-market constraints require design re-use at all levels of abstraction.

As a result of these changes, novel on-chip communication architectures that can effectively address all these issues are needed. Due to their limited bandwidth large capacitive load, legacy bus-based architectures fail to solve the above mentioned problems. While point-to-point (P2P) communication architectures may provide the required performance, the lack of scalability becomes a major issue for implementing complex applications. In contrast to these traditional methods, the recently proposed Networks-on-Chip (NoC) architecture provides a large bandwidth with moderate area overhead.

In this talk, we will discuss several key research problems in NoC design. Then, we will present our results on optimizing NoC architectures using application-specific long-range link insertion. Finally, we will present the prototyping efforts carried out as part of the SlicNetS project.


Umit Y. Ogras received his BS degree from Middle East Technical University, Turkey, in 2000 and his MS degree from The Ohio State University, Columbus, in 2002 both in electrical engineering. He is currently a Ph.D. candidate in the Department of Electrical & Computer  Engineering at Carnegie Mellon University, Pittsburgh, PA. His research focuses on communication-centric design methodologies for nanoscale SoCs, with a special interest on Networks-on-Chip communication architectures.