Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, September 12, 12:00-1:00 p.m. HH-1112


Subhasish Mitra
Stanford University

Built-In Soft Error Resilience for Robust System Design

Robust systems are expected to operate correctly in the presence of hardware failures, software malfunctions, malicious attacks and human errors. One design approach for such systems is to rely on conservative design, and limited use of fault-tolerance techniques. The conservative design approach imposes significant power and performance penalties. Hence, most future systems, not just high-end mainframes, will require built-in mechanisms for error correction, diagnostics, self-recovery and repair. Classical fault-tolerance techniques have limited applicability because they are very expensive, and often inadequate.

I will describe a new Built-In-Soft-Error-Resilience (BISER) technique for designing robust systems protected from radiation induced soft errors. In the past, soft errors were of concern especially for space applications. However, in sub-65nm technologies, soft error protection is necessary for terrestrial enterprise systems as well. BISER is an architecture-aware circuit design technique that corrects soft errors in flip-flops, latches and combinational logic. This enables more than an order of magnitude reduction in system-level soft error rate with negligible area and speed impact, and 5-9% chip-level power penalty. In comparison, classical redundancy techniques introduce 40-100% power, performance and area penalties.


Subhasish Mitra is an Assistant Professor in the Electrical Engineering Department of Stanford University. His research interests include robust system design, VLSI design and test, and design in future nanotechnologies. Prior to joining Stanford he was a Principal Engineer at Intel Corporation.

Prof. Mitra's research has seen wide-spread proliferation in the industry. His X-Compact technique for test compression has been used by more than 40 Intel products and is supported by major CAD tools. His most recent honors include the IEEE Circuits and Systems Society Donald O. Pederson Award, a Best Paper Award at the Intel Design and Test Technology Conference, a Best Paper Award nomination at the Design Automation Conference, a Divisional Recognition Award from Intel "for a breakthrough soft error protection technology," and the Intel Achievement Award, Intel's highest corporate honor, "for a breakthrough test compression technology." He is a 2006 Terman Fellow at Stanford.