Francois Jacquet ST Microelectronics

Design of SRAMs in Scaled CMOS Technologies

The emerging CMOS technologies, such as the 45nm and beyond, allow us to build more complex circuits containing hundred of millions of transistors, more than half of which are “embedded memories”. The SRAM design for such SoCs is driven by at least two main challenges – on one side the high frequency performances for processing data, and on the other side the low power requirements for “energy conservative” applications. The continuous CMOS technology scaling makes the SRAM cell development problem increasingly difficult in terms of sub-threshold leakage currents, gate oxide tunneling currents, and statistical variations in transistor characteristics. Furthermore, these same trends create a need for better immunity to soft error rate failures, as this reliability factor becomes more significant with each new technology as well.

In this presentation I will review the SRAM cell design problem, and describe the new challenges with technology scaling. The physical implementation and lithography issues will be addressed in detail, along with the “radiation induced soft error” problems that are more prominent with such layouts.

Bio:

Francois JACQUET was born in Corbeille Essones, France, in 1972. He received the M.S. degrees in electrical engineering from ENSERB, Bordeaux, France in 1996. In 1998, he joined the Central Research and Development, STMicroelectronics, Crolles, France, where he has been engaged on the design of eDRAMs and eSRAMs. His current research interests are cosmic-ray induced soft errors in SRAMs, and design solutions for low power and low leakage integrated circuits.