Siddharth Garg Carnegie Mellon University

Mitigating the Performance Impact of Within-die Variability Using GALS Architectures

Within-die process variability is expected to lead to significant performance yield loss in future scaled technologies. This can be attributed to the move towards shallower pipelines and greater levels of on-chip integration, thereby increasing the number and the delay variability of paths that need to meet strict timing constraints. In this context, previous studies have shown that there may be an entire process generations worth of performance lost at the 32-nm technology node.

In this talk, we will demonstrate how variability adaptive GALS (Globally Asynchronous Locally Synchronous) systems can help mitigate the adverse impact of process variability on system performance. Since the tie between clock frequencies and the performance metrics of interest to system level designers (such as throughput) is tenuous, especially for GALS architectures, we will outline an efficient and accurate analytical technique to estimate the yield of a given GALS design in terms of system throughput or latency. Finally, we will show how the proposed analysis technique can help system level designers make variability-aware architectural decisions (such as the granularity of GALS domain partitioning) early in the design process. A part of this talk will be presented at ICCAD 2006

Bio:

Siddharth Garg received his Btech degree in electrical engineering from the Indian Institute of Technology, Madras in 2004 and his MS degree, also in electrical engineering, from Stanford University in 2005. Since then, he has been working towards his Ph.D. in the department of Electrical and Computer Engineering at Carnegie Mellon University, advised by Professor Diana Marculescu. His research interests include variability modeling and mitigation techniques for embedded and high performance computing systems, with a specific focus on GALS architectures