Electrical & Computer Engineering     |     Carnegie Mellon

Tuesday, November 28, 12:00-1:00 p.m. HH-1112



Jason Brown
Carnegie Mellon University

Automated Standard Cell Library Analysis for Improved Defect Modeling

Testing typically considers only a logic-level model of the circuit under test. In complex ICs however, all physical nodes in the layout do not necessarily correspond to logic-level signals. Therefore, modern VLSI failure mechanisms that manifest as complex misbehaviors cannot be captured by traditional logic-level models. In order to reduce DPM (defective parts per million shipped parts), we must identify defects that are likely to occur and derive and model the faulty circuit behaviors that can result. Inductive fault analysis (IFA) techniques examine the critical area of a design to identify potential defect sites. This approach may require a significant amount of computation but provides a more accurate fault list, which consequently improves testing efficiency and product quality. To reduce computational complexity, critical area analysis is typically performed in a 'black-box' fashion where standard cells are removed from the layout and only inter-cell connections are considered as potential sites for defects. The primary difficulty involved with internal node defects is that their behavior is not easily modeled because an internal node does not always directly map to logic-level signals. Instead, many internal nodes exhibit transistor-level behavior and therefore cannot be captured using traditional logic-level models. A mapping between internal nodes of a standard cell and the logic level allows us to identify appropriate fault activation and error propagation conditions for internal node defects, thus allowing accurate fault models to be formed.

In this talk, we discuss a methodology to create a mapping between the physical nodes of a standard cell and the logic level. By identifying appropriate fault activation and error propagation conditions for each internal node, accurate fault models can be formulated. A fault modeling strategy for feedback bridging faults is described. Fault simulation results for ISCAS benchmark designs will be presented to show improved defect coverage.


Jason Brown received his B.S. degree in electrical engineering from Worcester Polytechnic Institute in 2002 and M.S. degree at Carnegie Mellon University in 2004. He has worked at companies such as Raytheon Electronic Systems, MIT Lincoln Laboratory, Atmel Corporation, and IBM Austin Research Lab. He is currently a Ph.D. candidate in the department of Electrical and Computer Engineering at Carnegie MellonUniversity, advised by Professor Shawn Blanton. His research interests include defect-based test, inductive fault analysis, and layout-driven diagnosis.