Electrical & Computer Engineering     |     Carnegie Mellon

Wednesday, April 6, 12:00-1:00 p.m. HH-1112


Gu-Yeon Wei
Harvard University

Research Potpourri & High-Throughput MAP Detector Architecture and Circuits

This talk presents a potpourri of research activities going on in the Mixed-Signal VLSI group at Harvard University.

High-speed link design is an important performance enabling component of next generation computing and communication systems. One of the main challenges is to minimize jitter in the clock generation and clock & data recovery (CDR) circuitry. This talk briefly describes a mixed PLL/DLL architecture that facilitates wide-range bandwidth adjustment of a clock generator to accommodate different noise conditions. Moreover, a methodology to use this clock generator in clock & data recovery is presented.

Wireless sensor networks is an exciting research area with myriad applications. This talk summarizes a holistic design approach that considers process technology, circuits, architecture, and applications to develop ultra low power processing nodes for wireless sensor network devices.

Lastly, this talk details a MAP detector architecture and circuits for magnetic recording applications. This detector implements a forward-only BJCR algorithm to approach theoretical limits of BER performance. The VLSI implementation uses skew-tolerant domino to achieve 1 Gbps throughput performance.


Professor Gu-Yeon Wei received his BS, MS, and PhD degrees in Electrical Engineering from Stanford University in 1994, 1997, and 2001, respectively. In August 2000, he joined Accelerant Networks Inc., a small high-speed links startup in Portland, Oregon, where he was a member of the design team for a 5-Gb/s backplane transceiver. Since January 2002, he Gu-Yeon has been at Harvard University as an Assistant Professor in Electrical Engineering. His interests include high-speed, low-power link designs; mixed-signal decoder circuits for communications; circuits for bio-sensor applications; and approaches for energy-efficient and robust computing via collaboration between circuits, architecture, and software.