Electrical & Computer Engineering     |     Carnegie Mellon

Wednesday, October 19, 12:00-1:00 p.m. HH-1112


Kim Yaw Tong
Carnegie Mellon University

Design and Synthesis of Regular Logic Bricks

In current nanoscale IC technologies, it is becoming increasingly difficult to achieve high enough production yield with affordable design cost. As technology scaling approaches physical limits, increased process variability coupled with various new challenges in sub-90nm technologies has rendered the benefits of further scaling questionable. New design methodologies are needed to extend the utility of nanoscale technologies. Here at Carnegie Mellon University, we proposed to implement circuits using extremely regular geometry patterns by way of a small collection of simple logic primitives. The regularity employed in this methodology reduces the number of unique layout patterns on ICs, thereby simplifying the application of Resolution Enhancement Techniques (RETs) for lithography. The extreme regularity also improves the control of process variablity and facilitates the co-optimization of process settings for logic and SRAM. In this talk, I will give an overview of the IC regularity research conducted in CMU. Following that, I will focus on one particular aspect of the research which concerns the generation of regular logic building blocks called Bricks. The methodology maps abstract boolean functions directly onto logic primitives using BDD-based functional decompositions.


Kim Yaw Tong received the B.S. and M.S. degrees in ECE from Carnegie Mellon University in 2002 and 2003 respectively. Currently, he is with the Department of Electrical and Computer Engineering, Carnegie Mellon University, PA, working towards the PhD degree under the guidance of Prof. Larry Pileggi. His research interests include various aspects of integrated circuit design and design automation. In particular, he has been exploring the benefits of regularity in IC design.