Jaejin Park Carnegie Mellon University

A 10-Gbps, 8-PAM Parallel Interface with Crosstalk Cancellation for Future Hard Disk Drive Channel ICs

As CMOS technology continues to scale for higher device speed, the supply voltage is reduced to approaching 1V and below. While faster logic improves the performance of DSP circuits in the channel IC of a conventional hard disk drive (HDD) system, low supply voltage makes it extremely difficult to implement the high-speed front-end analog interface circuits in the channel IC. In addition, as the data rate increases, using analog signaling through channel interconnect between the channel IC and the channel front-end IC becomes more vulnerable to noises in a conventional HDD system. To overcome this problem, we propose an alternative architecture by integrating the analog front-end circuits into the channel front-end IC with the Write Drive/Pre-amp. Although this alternative architecture makes implementing the analog interface circuits easier, it raises the challenge of transmitting multiple high-speed digital data streams from the front-end IC to the digital baseband circuits. Unless precautions are taken, the electro-magnetic interference (EMI) generated by this high speed digital channel interconnect may significantly degrade the noise floor seen at the read head.

This research addresses the opportunities and problems inherent to this modified architecture and the main goal is to design a high-speed digital signaling system for future HDD channel ICs. A transceiver consisted of a transmitter, interconnects, and a receiver, is being designed in a low supply voltage CMOS process. In order to increase the data transfer rate with less intersymbol interference (ISI), 8-level pulse amplitude modulation (PAM) scheme is adopted in our design. EMI and Crosstalk between the A/D converter (ADC) outputs and magnetoresistive (MR) element and its interconnect can also generate more noises at the read head. Therefore, a crosstalk and EMI reduction technique using 8-4-level PAM and a lookahead technique has been developed as part of this research. A 3-bit ADC, which means an 8-level PAM signal detection circuit in the receiver, is designed which includes quasi-integrators and latched comparators. Detailed circuits of the transmitter including a 3-bit D/A converter (DAC) and clock and data recovery (CDR) in the receiver are implemented. Test chips for this transceiver will be fabricated in a 0.13um CMOS process. The target data transfer rate of the transceiver is over 10 Gbps per channel and operating power supply voltage of the receiver is equal to 1V.

Bio:

Jaejin Park is a Ph. D candidate in Electrical and Computer Engineering at Carnegie Mellon University. He received a M.S. in Electrical Engineering from Seoul National University and a B.S. in Electrical Engineering from Korea Advanced Institute of Science and Technology (KAIST). His current research focuses on a high-speed I/O transceiver for HDD channel ICs. Before he joined CMU, he had been with Samsung Electronics, where he got involved in data converter design for image sensors, CD, DVD, and so on. His research interest is high-frequency/RF CMOS analog IC design for wireline and wireless communications.