Jeff Nelson Carnegie Mellon University

Extraction of Defect Density and Size Distributions from Product IC Test Results

Yield loss estimation for nanoscale integrated circuits is a central element of any design for manufacturability activity. There are many reasons for yield loss; some of them are well understood and have sufficiently accurate models, while others are very elusive and hard to characterize. Even those with well-developed models rely on process parameters that can be difficult to obtain. In particular, for short-type defects, the critical area yield model has proven to be very effective, but requires defect density and size distributions (DDSDs) for each metal layer in the process.

DDSDs can be very difficult to obtain and should be frequently monitored. In the past, only dedicated test structures and memories have been used to obtain DDSDs. In this talk, a technique for extracting the DDSD per process layer using only test results of the IC product is presented. A simulation experiment demonstrates how these distributions can be obtained without dedicating wafer space to exclusively monitor process parameters.

Bio:

Jeff Nelson received his B.S. degree in Electrical and Computer Engineering from Rutgers University in May, 2002, and his M.S. in Electrical and Computer Engineering from Carnegie Mellon University in December, 2003. Currently, he is a PhD candidate at Carnegie Mellon University under the guidance of Professors Shawn Blanton and Wojciech Maly. His research interests cover a spectrum of topics in manufacturing and test of integrated circuits, such as yield learning, defect modeling, diagnosis, and ATPG algorithms.