Natasa Miskov-Zivanov Carnegie Mellon University

Symbolic Analysis of Circuit Reliability

Due to the shrinking of feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, noise-related transient faults and interference from radiation. When high-energy neutrons or alpha particles hit the silicon bulk, they can result in a current pulse of very short duration, often called a single-event upset (SEU). These events may cause a bit flip in some latch or memory element. Additionally, a SEU may occur in an internal node of combinational logic and propagate to the latch. If latched, it results in a soft error. Traditionally, soft errors have been of greater concern in memories than in logic circuits, because of the small cell size of memories and the nature of memory - a SEU can immediately result in a soft error if it exceeds the critical charge stored in the cell. In contrast to this, three factors prevented logic from becoming more susceptible to soft errors: logical, electrical and latching-window masking. However, as technology continues to scale, logic circuits are becoming much more susceptible to soft errors. The trends toward reduced logic depth reduce the attenuation when SEU is propagating through the circuit. Smaller feature sizes and lower voltage levels allow lower energy particles to cause SEUs. Therefore, soft error rates in combinational logic are expected to become as important as soft error rates in memories.

In this talk, I will present a symbolic framework based on BDDs and ADDs that enables analysis of combinational circuits reliability from different aspects: output susceptibility to soft error, impact of individual gates on individual outputs and overall circuit reliability, and the dependence of circuit reliability on input patterns and on duration and amplitude of SEU. This is demonstrated by the set of experimental results, which show that the mean output error susceptibility can vary from less than 0.1% for large circuits and small glitches, up to about 30% for very small circuits and large enough glitches. The results obtained with the proposed symbolic framework are within 9% average error and 3900X speedup when compared to HSPICE detailed circuit simulation.

Bio:

Natasa Miskov-Zivanov is a graduate student in the Electrical and Computer Engineering Department at Carnegie Mellon University, working with Prof. Diana Marculescu. She received a M.S. in Electrical and Computer Engineering from Carnegie Mellon University in 2005 and a B.S. in Electrical Engineering and Computer Science from University of Novi Sad, Serbia and Montenegro in 2003. Her current research focuses on fault-tolerance in nanoscale designs and emerging technologies.