Electrical & Computer Engineering     |     Carnegie Mellon

Wednesday, October 5, 12:00-1:00 p.m. HH-1112


Peter A. Milder
Carnegie Mellon University

Automatic Generation of Customized Discrete Fourier Transform IPs

Reusable intellectual property (IP) cores of digital signal processing (DSP) kernels are important time-saving resources in DSP hardware development. Unfortunately, reusable IPs, however optimized, can introduce inefficiencies because they cannot fit the exact requirements of every application context. Given the well-understood and regular computation in DSP kernels, an automatic tool can generate high-quality ready-to-use IPs customized to user-specified cost/performance tradeoffs (beyond basic parameters such as input size and data format). By integrating the generator with easily-evaluated models of performance and resource usage, the user is able to quickly and accurately explore the generator's various options. Furthermore, the fast turnaround of the resource model allows it to be combined with a search algorithm such that the user could query automatically for an optimal design within stated performance and resource constraints.

In this talk, I will discuss how we use domain-specific knowledge of the Discrete Fourier Transform to generate and model highly-customized DFT IP cores and the advantages of this approach over a static IP library.


Peter A. Milder is a graduate student in the Electrical and Computer Engineering Department at Carnegie Mellon University. He works in the Spiral research group, and is advised by Professor James C. Hoe. Peter obtained a BS in ECE from Carnegie Mellon in 2004. His research interests include high-level hardware synthesis and customized DSP hardware.