Electrical & Computer Engineering     |     Carnegie Mellon

Thursday, March 17, 12:00-1:00 p.m. HH-1112


Pinaki Mazumder
University of Michigan

Design of Low Power, Low Noise and High-Speed VLSI Circuits Using Quantum MOS Technology

Recent advances in nano-fabrication technology have led to the development of new quantum electronic devices (QEDs) that can be now co-integrated with conventional Silicon (CMOS) as well as III-V technologies (InP, GaSb, and GaAs based heterostructure bipolar and FET devices). While conventional electronic circuits using CMOS and bipolar technologies achieve incremental improvements in speed and density through continual device scaling and process refinements, the quantum MOS and quantum tunneling devices with mesoscopic barrier structures, offer an order of magnitude improvements in both circuit speed and density for several reasons. These include: Quantum transport of charge carriers through double-barrier structures is inherently faster than field and potential effect devices, the use of "nano-pipelining" techniques that enable gate-level temporal overlapping of streamed data, and the use of multi-value coded signals due to folded-back device characteristics. The nonlinear electrical characteristics of these devices have also been utilized to improve the noise performance of domino gates, improve the circuit speed of TSPC flip-flops, reduce the power consumption of 1-T memory cells by eliminating the need for cell refreshing, improve the image-processing speed by analog cellular nonlinear networks, and so on. A suite of new CAD simulation and optimization tools needed to design quantum MOS and RTD/HEMT circuits has been developed at the University of Michigan. In addition to introducing innovative circuit topologies using these devices, the talk will describe the key design ideas behind these new CAD tools.


Pinaki Mazumder received his Ph.D. from the University of Illinois at Urbana-Champaign in 1988. He is at present a Professor of Electrical Engineering and Computer Science at the University of Michigan. He had worked for six years in industrial R&D centers that included AT&T Bell Laboratories, where in 1985 he started the CONES project, the first C modeling based VLSI synthesis tool, and India's premiere electronics company, Bharat Electronics Ltd., where he had developed several high-speed and high-voltage analog integrated circuits intended for consumer electronics products. He has published over 200 technical papers and 4 books on various aspects of VLSI research works that include current problems in very deep submicron CMOS VLSI design, CAD tools and circuit designs for emerging technologies like Quantum MOS and RTD/HEMT, semiconductor memory systems, and physical synthesis of VLSI chips. Dr. Mazumder was a recipient of Digital's Incentives for Excellence Award, BF Goodrich National Collegiate Invention Award, National Science Foundation Research Initiation Award, and DARPA Research Excellence Award. In January 1999, he had become an IEEE Fellow for his contributions to the field of VLSI.