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Wojciech Maly
Carnegie Mellon University
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Wafer Scale Integration, Multi-Chip Module (MCM), and 3-D integration are examples of system integration strategies, which have been investigated in the past as an alternative to traditional monolithic approaches. This presentation discusses a new - so called "2.5-D"- system integration scheme. As illustrated in Fig. 1 this schema involves 3-D stacking of monolithic chips with vertical interconnects between adjacent chips. It's key feature are: (a) passive, self-alignment assembling technology and (b) an incremental and hierarchical testing methodology that allows "reworking" (so that a faulty part could be replaced during the assembling process).
Fig.1. 2.5D 16 microprocessor system
Intuitively, the 2.5-D scheme offers many advantages: i) reduced system size and weight; ii) mixed-technology integration; iii) systematically shortened wire length and thus performance gain as well as power saving; and iv) new opportunities for reuse. We have built an analysis framework to verify the above claim and compare different integration schemes. As a key figure of merit we have chosen total silicon area, which needs to be fabricated to build a working system. Our model takes into account both manufacturing cost and testing cost. In the presentation the results of analysis will be discussed in detail. The conclusion is that the 2.5-D integration scheme offers considerable cost/performance advantages over other 3D and 2D technologies but requires investment in stacking and design technologies.
Wojciech Maly received the M.Sc. and the Ph.D. degrees from Technical University of Warsaw from the Institute of Applied Cybernetics, Polish Academy of Sciences, Warsaw, Poland, in 1970 and 1975, respectively. Since 1983, he has been with Carnegie Mellon University, where he is a Whitaker Professor of Electrical and Computer Engineering.
Dr. Maly's research interests have been focused on the interfaces between VLSI design, testing and manufacturing with the stress on the stochastic nature of phenomena relating these three VLSI domains.
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