Electrical & Computer Engineering     |     Carnegie Mellon

Thursday, April 28, 12:00-1:00 p.m. HH-1112


Rao Desineni
Carnegie Mellon University

Diagnosis of Arbitrary Defects in VLSI Circuits

Quick time-to-market demands for integrated circuits (ICs) mandate fast and accurate diagnosis to identify the potential defects and their root causes when the ICs fail testing. Software-based diagnosis has traditionally been used to assist the complex and time-consuming physical failure analysis (PFA) process by providing target locations (gates, sub-circuits, or nets). However, the effectiveness of this two-stage approach is rapidly diminishing with the continuous circuit miniaturization and increasing complexity of the manufacturing process and packaging technology – factors that are rendering the PFA process ever more difficult. As a result, software-based fault diagnosis is expected to increasingly supplement the physical characterization and inspection process to find yield loss problems.

Fault diagnosis is a logical search to determine the potential sources of error (defects) using the IC netlist and the knowledge of how the IC failed for a given input stimulus. In this talk, an overview of the past and current fault diagnosis techniques will be presented. A new approach to fault diagnosis that focuses upon identifying the accurate behavior of defects in addition to their locations will be presented. The major differences and advantages of our approach over other diagnosis techniques will be discussed. Specifically, it will be shown how our approach increases the overall accuracy of diagnosis by utilizing the layout-level dependencies of IC defects. High accuracy of fault diagnosis directly translates into reduction (or elimination) of PFA effort, which can significantly cut both the cost of yield learning as well as the time-to-market.


Rao Desineni is a Ph.D. student working with Prof. Shawn Blanton in the Electrical and Computer Engineering Department at CMU. He received his M.S. degree in ECE from CMU in 2001. Prior to his M.S., Rao worked for a year as a hardware design engineer at IBM Global Services, Bangalore, India. His research interests lie in various aspects of IC test and diagnosis including fault diagnosis, defect-based testing, defect modeling and ATPG algorithms.