Electrical & Computer Engineering     |     Carnegie Mellon

Thursday, March 24, 12:00-1:00 p.m. HH-1112


Tim Callahan
Carnegie Mellon University

Automatic Utilization of a Reconfigurable Coprocessor

The idea of augmenting a microprocessor with reconfigurable hardware as a coprocessor has been around for a long time. Yet a key obstacle to widespread acceptance of such systems is the difficulty in programming them easily and effectively. Ideally, there would be a compiler that would take a sequential program written in C, find the parts of it amenable to hardware acceleration, find and enhance the instruction-level parallelism in these regions, and synthesize the resulting spatial datapath for each region -- and perform all these tasks in time comparable to software compilation.

The pursuit of this goal led to the compiler flow described in this talk. The flow borrows from VLIW compilation techniques based on the hyperblock. The commonly-executed paths in each loop are selected to form a hyperblock. The basic blocks in the hyperblock are merged using if-conversion, whereby control flow is eliminated and predicated execution is instead used. The result is a data-flow graph (DFG) in which data producer / consumer relationships are made explicit via edges; this is similar to static single assignment (SSA) form and derives similar benefits for implementation of standard and novel optimizations. A module mapping/generating technique groups DFG operations to form specialized function units, and the resulting circuit is then pipeline scheduled to overlap the execution of successive iterations as much as possible. Streaming memory accesses are also exploited if provided by the target platform. Results and experience from compiling the SPECint benchmark suite will be given.


Tim Callahan received his PhD and Masters degrees in Computer Science from UC Berkeley; his Diploma in Computer Science from Cambridge University; and his Bachelors of Electrical Engineering from the University of Minnesota. While at UC Berkeley he interned at Synopsys, where his thesis work became the basis for the Nimble Compiler project. After finishing at Berkeley, he worked at SRC Computers improving the compiler for their Pentium / Xilinx FPGA platform. Tim is now a systems scientist in the Phoenix research group at CMU and is co-teaching "Compilers for Modern Architectures" with Prof. Seth Goldstein.