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Wednesday, January 28, 1:30-2:30 p.m. HH-1112
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Yang Xu
Ph.D. Candidate of ECE
Carnegie Mellon University
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ORACLE: Optimization with Recourse of Analog Circuits including Layout Extraction
Long design cycle due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens for technologies below 100nm, the high cost of design and multiple manufacturing spins causes fewer products to have the volume required to support full custom implementation. Design reuse and analog synthesis methodologies can substantially address the mixed-signal IC design cost and risk challenges. For a given circuit topology and the custom specifications, simulation based optimization and equation based optimization have been quite effective for automating the design process. However, the large process parameter variability that is evident for nanoscale technologies along with the complex nature of parasitic coupling can cause the design risk to remain quite high, even for the best synthesis approaches.
In this talk, a new methodology ORACLE is discussed, which incorporates the shared-use and reuse benefits of configurable circuits, while offering performance that is comparable to a fully customized design. Instead of a flow to optimize a circuit for a single application, we propose an optimization framework that supports a methodology for configurable designs that "share" common structures. These common structures can then be pre-characterized for subsequent application-specific customization thereby allowing the second stage of optimization to accommodate extracted layout realities. We formulate our configurable design problem as an optimization with recourse problem. Using a two-stage geometric programming with recourse (GPR) approach, ORACLE solves for both the globally optimal shared and application-specific variables. Concurrently, we demonstrate ORACLE for novel metal-mask configurable designs, where a range of applications share common underlying structure and application-specific customization is performed using the metal-mask layers. The silicon validation of the metal-mask configurable designs is realized using a 0.25µm 47GHz fT IBM 6HP SiGe BiCMOS process technology.
Bio
Mr. Yang Xu received the B.S. and M.S. degrees in electronics engineering from Fudan University, Shanghai, P.R. China, in 1997 and 2000, respectively. He is currently working toward the Ph.D. degree at Carnegie Mellon University, Pittsburgh, PA. His research interests include design and optimization of RF/analog and mixed-signal circuits and systems, circuit noise analysis and macromodeling.
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