Electrical & Computer Engineering     |     Carnegie Mellon

Wednesday, July 14, 12:00 - 1:00pm HH-1114


Hank Walker
Texas A&M University

Defect-Based Delay Test and Statistical Timing Analysis of Integrated Circuits


In more advanced technologies an increasing proportion of defects manifest themselves as small delay faults, that is, delay increases that will only cause the longest paths propagating through them to fail. An example of such a defect is a resistive via between two metal interconnect layers. Traditionally such small delay faults have been detected by functional testing, and to a lesser degree by path delay testing. However such approaches have become too costly. In conjunction with Weiping Shi, we have developed a defect-based delay fault approach. We have developed delay fault models that combine the effects of resistive opens and shorts, coupling noise and parametric process variation, and developed the CodSim fault simulator and CodGen ATPG to apply them. Process variation means that any one of a number of paths could be the longest path through a particular fault site, so we generate the K longest sensitizable paths through each gate (KLPG). We then use process correlation to trim the path set with the PASTA tool. Typically only a few paths must be tested through each gate. We have demonstrated CodGen on industrial chips of up to 1.2M gates, with test sets that are anywhere from one half to twice the size of commercial transition fault test sets. We are working with two companies to collect industrial production data on the effectiveness of KLPG test sets. In current research we are incorporating the effects of supply noise and temperature into delay test.

Defect-based delay test is closely related to statistical static timing analysis (SSTA), in that the timing of a defect-free circuit is a function of process variation, coupling and supply noise, and temperature variation. The primary difference is that SSTA is vectorless, and so cannot by itself determine path sensitization, it must be very fast, and it must assume the worst case. One challenge is that the worst case may be much worse than the worst real case. We will discuss our initial efforts in applying our delay test research to SSTA.


Hank Walker received his BS in engineering from Caltech. He then spent 14 years at Carnegie Mellon University, first receiving his MS and PhD in computer science, then as research faculty and CAD Center assistant director in the Dept. of Electrical and Computer Engineering. He is currently a faculty member in the Dept. of Computer Science at Texas A&M University. He has also worked for Hughes Aircraft, Digital Equipment and IBM. His research interests include defect-based test, defect diagnosis, yield modeling and timing analysis.