Larry Pileggi Carnegie Mellon University

Structured Layout for Extreme Scaled CMOS

As CMOS scales to finer feature sizes it becomes increasinglychallenging to print the transistor and interconnect patterns so that the resulting circuits have acceptable functional and parametric yield. For this reason we have explored the use of regular fabrics for defining the underlying silicon geometries that will facilitate better control and prediction of the patterning for nanoscale feature sizes. Mapping logic onto regular fabrics suggests the use of more regular circuits. While we expect some area and performance penalty for these regularity constraints, our work has found that careful selection of the regular logic can mitigate or even overcome any penalties. By developing new methodologies and physical mapping algorithms to exploit the newfound predictability, we believe that the performance of regular logic can surpass that of seemingly more flexible standard cells. Furthermore, it is expected that standard cells will ultimately lose this sizing flexibility as manufacturing realities force us toward more regular geometry patterns and new transistor structures. In this presentation we describe a first-step toward more regular logic fabrics in terms of a "regular logic brick" design methodology whereby a brick is a fixed footprint logic element that shares regular patterns with all other bricks. We show some early result comparisons with standard cells, and further describe our ongoing work toward constructing and mapping to application-specific logic bricks from an RTL netlist.

Bio:

Larry Pileggi is the Tanoto professor of electrical and computer engineering and the Director of the Center for Silicon System Implementation at Carnegie Mellon University. From 1984 through 1986 he was an IC designer for Westinghouse Research and Development, and in 1986 was recognized with the corporation's highest engineering achievement award. In 1989 he received his Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University. He began his academic career as a faculty member at the University of Texas at Austin in 1989, then joined the faculty at Carnegie Mellon University in 1995. His research interests include various aspects of digital and analog design and electronic design automation (EDA). He has received various awards including the 1990 and 1999 Best CAD Transactions Paper Awards, a 2003 DAC best paper award, an NSF Presidential Young Investigator Award, the 1991 and 1999 Semiconductor Research Corporation Technical Excellence Awards, and an SRC 1993 Invention Award. He is a co-author of two books, has published over 175 refereed conference and journal papers, and holds 11 U.S. patents. He is a fellow of IEEE.