Electrical & Computer Engineering     |     Carnegie Mellon

Friday, November 12, 2:30-3:30 p.m. HH-1112


Hiroshi Nakamura
The University of Tokyo


Dynamic Processor Throttling for Power Efficient Computing


We are currently conducting a research project for a 'High-Performance and Low-Power GALS Processor with Dynamic Voltage Scaling.' In this talk, we introduce the project briefly at first, and then present a dynamic processor throttling (DPT) technique as the first-step of this research.

DPT is a novel hardware-based DVS technique which focuses on performance balance between processor and memory. When performance imbalance is detected, DPT tries to adjust the clock frequency and the supply voltage to a well-balanced point. We show its micro-architecture mechanisms and evaluation results. The results reveal that DPT outperforms a conventional cache-miss driven DVS technique both in performance and energy.


Hiroshi Nakamura received the BE, ME, and Ph.D. degree in Electrical Engineering from the University of Tokyo in 1985, 1987, and 1990 respectively. From 1990 to 1996, he was a faculty member of the Institute of Information Sciences and Engineering at the University of Tsukuba. He was a visiting associate professor at the University of California, Irvine from 1996 to 1997 and is currently an Associate Professor of the Research Center for Advanced Science and Technology at the University of Tokyo. His research interests include high-performance and low-power processor architecture, dependable computing, and VLSI design. He received the best paper award from the Information Processing Society of Japan (IPSJ) in 1994 and the Sakai Special Researcher Award from IPSJ in 2002.