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Wednesday, February 18, 1:30-2:30 p.m. HH-1112
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James Ma
Ph.D. Candidate of ECE
Carnegie Mellon University
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Large-Scale Placement by Grid-Warping
Circuit placement is a critical step in the physical realization of any large design. Despite roughly two decades of impressive progress, the problem remains an important one to focus on. Much of the final performance — size, speed — of a modern IC implementation is determined by its placement. In this talk we will describe a novel placement algorithm. Different with most existing placement methods, our idea is strikingly simple: rather than move the gates to optimize their locations, we elastically deform a model of the 2-D chip surface on which the gates have been quickly and coarsely placed, "stretching"it until the gates arrange themselves to our liking. Put simply: we move the grid, not the gates. This strategy transforms a high-dimensional optimization task that relies on simple cost function into a surprisingly low-dimensional optimization problem that determines the deformation of the placement grid, thereby leveraging powerful nonlinear methods amenable to any well-behaved objective function we like. We call this placement by grid-warping. A preliminary implementation, Warp1, is already competitive with most recently published placers.
Bio
James Ma obtained his BS degree in Electrical Engineering from Fudan University, Shanghai, P. R. China in 2000 and MS degree in Electrical and Computer Engineering from University of Wisconsin-Madison in 2002. He is currently a PhD candidate under the guidance of Prof. Rob A. Rutenbar at the Department of Electrical and Computer Engineering, Carnegie Mellon University. His research interests include physical design automation, and interconnect analysis and optimization.
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