Electrical & Computer Engineering     |     Carnegie Mellon

Thursday, October 7, 12:30 - 1:30pm HH-1112


Satoshi Inaba
Toshiba Corporation

Key Technologies for Advanced CMOS Devices Beyond 65 nm Node Generation


Recently, the scaling limit of MOSFET has been discussed both from technical and economical point of view. Many issues should be discussed and overcome to achieve higher performance in CMOS LSI's with device size miniaturization. In the first half of this presentation, we will briefly review the future technological prospects for 65 nm node CMOS or beyond. The discussion will be extended to carrier mobility enhancement, ultra-thin gate dielectrics and new MOSFET device structures such as SOI or double gate devices.

The second half of this presentation, we would like to introduce new CMOS Device structure, Silicon on Depletion Layer CMOS (SODEL CMOS) to achieve high performance and low power logic circuit. SODEL CMOS is fabricated on a bulk silicon wafer and it has an artificial depletion layer made by p / n- / p junction beneath a channel region, which works as an insulator like a buried oxide (BOX) in SOI MOSFETs. Thanks to smaller Cj and smaller body effect, like in PD-SOI CMOS, SODEL CMOS shows the better performance compared to conventional bulk CMOS devices. This part will be the review of the paper presented at IEEE CICC 2004.


Satoshi Inaba was born in Kanagawa, Japan in 1964. He received the B.S. degree in applied physics in 1988, and the M.S. degree in physics in 1990 both from Waseda University, Tokyo, Japan. In 1990, he joined the ULSI Research Center, Toshiba Corporation, Kawasaki, Japan, where he had been engaged in the research and development of 0.10 m gate length CMOS. From 1998 to 2000, he was with IBM-Siemens-TOSHIBA 256M bit DRAM Development Alliance, Hopewell Junction NY, and was working both for 0.175 m / 0.15 m DRAM support devices. He is currently a member of SoC Research and Development Center, Toshiba Corporation Semiconductor Company, Yokohama Japan. His current research interests are the device physics and fabrication technology of the high speed and low power dissipation sub-50 nm gate length CMOS devices. He is also interested in the physics of electron transport phenomena in very small Si-based electron devices. Mr. Inaba has served as a technical subcommittee member of International Electron Devices Meeting (IEDM) from 2003 to 2004, and International Conference on Solid State Devices and Materials (SSDM) from 2002 to 2004. He is a member of the Physical Society of Japan and the Japan Society of Applied Physics.