Electrical & Computer Engineering     |     Carnegie Mellon

Friday, October 29, 3:00 - 4:00pm HH-1112

 

Ran Ginosar
Israel Institute of Technology

Synchronization in Multiple-Clock-Domain Systems on Chip

 

Different SoC situations require different synchronizers, which all attempt to achieve zero-latency interconnects between different clock domains. Multi-synchronous domains (using same frequency but arbitrary phase clocks) employ Adaptive Synchronizers. Periodic domains (having different frequency clocks) can use Predictive Synchronizers. When per-domain dynamic voltage and frequency scaling is employed, the synchronizers need to adapt to changing clocks. We investigate the synchronizers, measure them, and also attempt their formal verification. In addition, we investigate the basic two-flop synchronizer and discuss novel metastability measurement techniques and their limitations. The talk will conclude by refuting some common synchronization fallacies.

Bio:

Ran Ginosar received his EE/CS BSc at the Technion--Israel Institute of Technology in 1978 and his PhD at Princeton University in 1982. He has conducted research at Bell Labs and at Intel Corporation. He heads the VLSI Systems Research Center of the Technion's EE and CS departments. His research interests include synchronization, asynchronous logic, and VLSI architecture of mixed-signal Neuroprocessors for brain research and clinical applications.