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Wednesday, February 4, 1:30-2:30 p.m. HH-1112
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Georges Gielen
Professor
Katholieke Universiteit Leuven
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Analog Performance Modeling for Analog Circuit Synthesis
Analog circuit synthesis is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient methods that can handle design hierarchy, and implies the need for hierarchical analog performance modeling. This presentation will discuss recent developments in this area, including the application of new techniques such as support vector machine modeling.
Bio
Georges G.E. GIELEN received the MSc and PhD degrees in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 1986 and 1990, respectively. In 1993, he was appointed as a tenure research associate of the Belgian National Fund of Scientific Research and at the same time as an assistant professor at the Katholieke Universiteit Leuven, where he became full-time full professor in 2003.His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation (modeling, simulation and symbolic analysis, analog synthesis, analog layout generation, analog and mixed-signal testing). He is coordinator or partner of several (industrial) research projects in this area. He has authored or coauthored two books and more than 200 papers in edited books, international journals and conference proceedings. He is a Fellow of the IEEE.
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