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Carolyn Block, Ph.D.
Technology and Manufacturing Group
Intel Corporation
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Silicon research at Intel has historically been driven by Moore's Law - the ability of the industry to double the number of transistors per integrated circuit every 18-24 months. This continues to be a motivating factor for logic research and development, and this talk will focus on several challenges associated with transistor scaling. The research, development, and high volume manufacturing strategies for Intel will be presented. In addition, research results on transistor scaling will be addressed, including the transition from a SiO2-based gate dielectric to the high k metal gate system. With transistor scaling, new challenges arise in interconnects and packaging that did not exist with lower transistor densities. Specifically, power consumption and RC delays in the wiring play an increasing role in limiting the ultimate performance of the microprocessor. Some of the challenges associated with these areas will be discussed, including ultra low-k dielectric integration and metal line resistance.
Carolyn Block joined Intel in 1998 in the Portland Technology Development organization. As a process engineer, she focused on the development of thin film deposition techniques for copper interconnects in the 0.13um, 90nm and 65nm technology nodes. In 2002, she transitioned to the Components Research organization and currently leads efforts in defining and executing collaborative technology development programs with external sources. She received a BS degree from Carnegie Mellon University and a Ph.D. from Northwestern University, both in Materials Science and Engineering.
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