Electrical & Computer Engineering     |     Carnegie Mellon

Wednesday, April 9, 12:00-1:00 p.m. HH-1112


Kim Yaw Tong
Carnegie Mellon University

Via Patterned Gate Array (VPGA)

The design and manufacturing costs of standard-cell-based ASIC are increasing so rapidly that fewer products have sufficient volume to justify the high non-recurring engineering (NRE) costs. As a result, more designs are relying on programmable devices such as FPGAs (field programmable gate arrays) that have low NRE costs but with inferior power-delay performance. As a compromise, a Via Patterned Gate Array (VPGA) has been proposed as a new regular logic fabric that is customizable by a few via masks to provide design flow simplicity and NRE costs comparable to a FPGA, but with power-delay performance closer to a standard cell design.

This talk provides an overview of the VPGA project, and provides some specific details on my work for developing lookup table (LUT) topologies that optimize power-delay performance in terms of the via patterning methodology.

Kim Yaw Tong received the B.S. degree in ECE from Carnegie Mellon University in 2002. Currently, he is with the Department of Electrical and Computer Engineering, Carnegie Mellon University, PA, working towards the M.S. degree under the guidance of Prof. Larry Pileggi. His research interests include various aspects of integrated circuit design.