Electrical & Computer Engineering     |     Carnegie Mellon

Wednesday, March 12, 12:00-1:00 p.m. HH-1112


Russell Tessier
University of Massachusetts, Amherst

aSoC: A Scalable, On-Chip Communication Architecture

A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease-of-implementation have became important aspects of the design process. This talk describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive System-On-a-Chip, and supporting software for application mapping. This architecture exhibits hardware simplicity and optimized support for compile-time scheduled communication. To illustrate the benefits of the architecture, four high-bandwidth DSP applications including an MPEG-2 video encoder have been mapped to a prototype aSOC device using our design mapping technology. Through experimentation it is shown that aSOC communication outperforms a hierarchical bus-based SoC approach by up to a factor of 5. A VLSI implementation of the communication architecture indicates clock rates of 400MHz in 0.18 micron technology for sustained on-chip communication.

Russell Tessier is an assistant professor of electrical and computer engineering at the University of Massachusetts, Amherst. He received the B.S. degree in computer engineering from Rensselaer Polytechnic Institute and M.S. and Ph.D. degrees in electrical engineering from MIT. Dr. Tessier is a founder of Virtual Machine Works, a logic emulation company, and was the Program Chair for FPGA'2003.