Electrical & Computer Engineering     |     Carnegie Mellon

Wednesday, December 3 , 12:00-1:00 p.m. HH-1112


Emil Talpes
Carnegie Mellon University

Flywheel: Enabling Performance Increase and Power Efficiency by Using Multiple Speed Pipelines

During the past decades, microprocessor performance improved at a rate of 50 to 60% per year sustained by better process technologies and increasingly parallel designs. In trying to sustain a similar trend, one of the most important problems faced by designers is the poor scalability of current solutions with increased clock frequencies and wider pipelines. Internal processor structures scale differently with decreasing device sizes. While in some cases the access latency is determined by the speed of the logic circuitry, for others it is dominated by the interconnect delay. Furthermore, while some modules can be superpipelined with relatively little performance loss, others must be kept atomic.

One microarchitectural component that is poorly scalable is the Issue logic, containing the Wake-up/Select loop. In order to sustain back-to-back scheduling for dependent instructions, this loop cannot be pipelined and limits the overall achievable frequency.

This talk presents a possible solution to this problem. Using multiple clock domains and decoupling the issue mechanism from the rest of the pipeline, performance can be improved beyond the limit imposed by the single clock design methodology. First, synchronizing instructions that enter and leave the Issue Window with different clock signals allows for faster speeds in the front-end at the expense of small synchronization latencies. Second, using an Execution Cache for storing instructions that are already scheduled allows for bypassing the issue circuitry and thus allows for clocking the execution core at higher frequencies. Combined, these two mechanisms should result in a significant performance increase without requiring a completely new scheduling mechanism.

Emil is a Ph.D. student in the Department of Electrical and Computer Engineering at Carnegie Mellon. He received his BS in Computer Science from the Polytechnical Institute of Bucharest, Romania. He works with Diana Marculescu on research focusing on Computer Architecture and Low Power.