Electrical & Computer Engineering     |     Carnegie Mellon

Wednesday, February 26, 12:00-1:00 p.m. HH-1112


JoAnn Paul
Carnegie Mellon University

Layered, Multi-Threaded, High-Level Performance Design for Programmable Heterogeneous Multiprocessor SoCs

A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detailed design. Future SoCs will be more like Programmable Heterogeneous Multiprocessors (PHMs) than RTL-based ASIC designs or ISA-based processor designs; the absence of a modeling abstraction such as RTL or ISA makes high-level modeling especially challenging. This talk motivates and evaluates a high-level, layered software-on-hardware performance modeling environment called MESH. The validity of the MESH modeling abstractions is established by comparing the outcome of the high-level model with a corresponding low-level, cycle-accurate instruction set simulator. We model a network processor and show that both high and low level models converge on the same architecture when design modifications are classified as good or bad performance impacts.

JoAnn M. Paul is Research Faculty in the Department of Electrical and Computer Engineering at Carnegie Mellon University since 2000. Prior to that she was a Visiting Assistant Professor there since 1997. She received her Ph.D. in Electrical Engineering from the University of Pittsburgh, publishing her research in a unique 3-D pipeline for L-U Factorization with minimal latency and maximum throughput using processing elements of two computations per cycle. Her industrial experience (including positions at Tartan, Formtek, and Westinghouse) has included design of hardware and software for safety-critical systems and design of real-time and debug kernels. She is a Licensed Professional Engineer (PA). Her research focus is the modeling and design abstractions for Programmable Heterogeneous Multiprocessor SoCs, where she is a part of the MESH team at CMU.