Electrical & Computer Engineering     |     Carnegie Mellon

Monday, April 28 , 3:00-4:00 p.m. HH-1112


Azad Naeemi
Georgia Institute of Technology

Optimal Global Interconects for Gigascale Integration

As the minimum feature size used to fabricate integrated circuits scales down, the number of transistors within a chip grows exponentially, which improves the functionality of future chips. Furthermore, downscaling the size of transistors lowers their latency, which enables higher clock frequencies. Interconnects, however, do not obey this rule; downscaling the cross-sectional dimensions of a wire increases its latency. This problem is even more serious for global interconnects since their lengths do not scale down with technology. Hence, the wiring resource is becoming more precious as compared with the transistor resource, and the design of GSI chips should therefore shift from transistor-centric toward interconnect-centric.

In this talk, a new interconnect-centric methodology is proposed to optimize the design of global interconnects by simultaneously maximizing data flux density and minimizing latency. Data flux density, which is the product of interconnect bandwidth and reciprocal pitch, determines the total number of bits per second that global interconnects can potentially transfer. This optimal design also offers the best trade-off between energy dissipation and data flux density. Interconnect crosstalk and dynamic delay variation as well as silicon area used for repeaters are reduced substantially.

Azad Naeemi received his B.S. Degree from Sharif University, Tehran, Iran in 1994, and his M.S. degree from Georgia Institute of Technology, Atlanta, Georgia in 2001, both in electrical engineering. Currently he is pursuing the Ph.D. degree in the school of Electrical and Computer Engineering at Georgia Institute of Technology under supervision of Professor James Meindl.

From 1994 to 1999, he taught at the Khazra'i Institute and worked as a design engineer at Partban and KCR Companies in Tehran, Iran. His current research interests are in the areas of interconnect modeling and optimization, impact of inductance on GSI interconnects, far inductive noise modeling, and chip-package co-design methodologies.

In spring 2000, he was awarded the Colonel Oscar Cleaver Prize, which recognized him as the outstanding graduate student in the school of Electrical and Computer Engineering at the Georgia Institute of Technology.