Subhasish Mitra Stanford University

X-Compact + Xpand: A Low-Cost High Quality Scan Test Solution

We present a novel test data compression architecture capable of achieving almost exponential reduction in scan test data volume and test time while allowing use of commercial Automatic Test Pattern Generation (ATPG) tools. It tolerates presence of sources of unknown logic values (also referred to as X's) without compromising test quality and diagnosis capability for most practical purposes. The architecture has been implemented in several industrial designs.

Bio
Subhasish Mitra received Ph.D. in Electrical Engineering from Stanford University in 2000. He is currently a Senior Staff Engineer at Intel Corporation and a Consulting Assistant Professor in the Electrical Engineering Department of Stanford University. At Intel, Dr. Mitra works on DFX - Design for Testability, Reliability, Manufacturability and Debug. At the Stanford Center for Reliable Computing (CRC), he is an Associate Director and is currently involved with the Stanford CRC test chip experiment project. Before that, he was the leader of the DARPA-sponsored Stanford CRC ROAR (Reliability Obtained by Adaptive Reconfiguration) project. During 2000-2001 he provided consulting at Agilent Technologies in their System Chip Testing program. He spent a summer at Ambit Design Systems (now part of Cadence Design Systems) to integrate a special synthesis algorithm developed by him into Ambit's BuildGates tool. Dr. Mitra's research interests include robust computing, VLSI testing, VLSI CAD and computer architecture. Dr. Mitra received gold medals for being the top student in the School of Engineering in the undergraduate and M. Tech levels. His recent awards include a Recognition Award at Intel for developing a "break-through scan compaction methodology for test cost reduction", and the IEEE VLSI Test Symposium Best Panel Award.