Mahim Mishra Carnegie Mellon University

Defect Tolerance at the End of the Roadmap

With feature sizes shrinking towards the single-digit nanometer domain, the defect density in manufactured devices is expected to show a sharp increase. This is expected to be true irrespective of the technology used: Extreme Ultraviolet Lithography, Chemically Assembled Electronic Nanotechnology (CAEN) or some other. Tolerating these high defect levels will require us to rethink the abstractions used in computing devices today, at the levels of devices, circuits, architectures and compilation tools. In particular, it may not be possible to maintain the abstraction of a defect free device: exposing these defects to the higher layers may be the only way to achieve scalable defect tolerance.

In this talk, I briefly overview work being done in the Phoenix group to develop the new abstractions and tools required to achieve defect tolerance. Our work centers around asynchronous reconfigurable devices and dynamic place-and-route, and has particular applicability to CAEN. Reconfigurability allows one to tolerate defects in the fabric by configuring circuits around them. This requires information about the location of the potentially large number of defects. Obtaining this information requires testing techniques significantly different from the ones used today in practice. I shall describe in detail some initial work we have done towards the development of such a testing technique, and show some simulation results that demonstrate the scalability of our approach.

Bio
Mahim received his B.Tech. degree in Computer Science and Engineering from the Indian Institute of Technology, Kanpur in 2001. Currently he is pursuing the Ph.D. degree in Computer Science from CMU, where he is part of the Phoenix group under the supervision of Professor Seth Goldstein.