Electrical & Computer Engineering     |     Carnegie Mellon

Friday, October 3 , 1:00-2:00 p.m. Singleton Room, Roberts Hall


Anne Meixner
Intel Corporation

High Volume Manufacturing Integrated Circuit Testing: Overview and Today's Challenges

Like the chair you are sitting on, IC's are tested before shipped to customers. Testing screens out bad product be the obvious- not functioning or subtle- reliability fails. Today's VLSI products are complex parts composed of 10's of millions of transistors (.13 micron CMOS technology with 7 layers of metal) functioning at clock rates over 1 Giga Hertz. A view of a recent Intel microprocessor layout draws analogies to a small city. The testing of this "small city" is limited to about 300 primary inputs/outputs. The modern microprocessor contains a large SRAM, high speed clocking, complex logic, and higher speed I/O all of which require specialized testing to meet the high quality demands of less than 400 Defects Per Million. This talk introduces the audience to IC testing terminology, Design for Test (DFT) and basic flows used in a High Volume Manufacturing environment. Then current challenges in the industry will be listed with some in depth discussion on I/O test challenges for microprocessors. Note, eight years ago the I/O data rate was at 66 Mega Transfers per Second (MTS). Today, the data rate is 400 MTS and 1 GTS is on the horizon. For communication ICs which have low volumes and high profit margins, expensive test solutions are often pursued. Such test solutions are not feasible for computer IC's, which have volumes in the 10's of millions per year and much lower profit margin.

Anne Meixner works in STTD within the Strategic Test Methods Development group. Based at the Oregon site, Anne has 8 years with Intel and another 8 years of IC based test experience. In December 1993, Anne earned her PhD from Carnegie Mellon University in Electrical and Computer Engineering. For the past 5 years Anne has been involved in the development of I/O test methods. She has published several DTTC papers and two International Test Conference (ITC) papers. She co-authored a 1996 ITC paper on Weak Write Test Mode which was awarded Best paper of the conference. She currently is serving her third term on the ITC program committee. To balance her life at Intel, Anne teaches Alpine skiing from Dec March at Mt. Hood and volunteers with her husband, Mike, at their neighborhood farmer's market from May to Oct.