Electrical & Computer Engineering     |     Carnegie Mellon

Wednesday, September 17 , 12:00-1:00 p.m. HH-1112


Jack Kenney
Analog Devices Inc.

Clock and Data Recovery Circuit of 10Gbps Serial Data in 0.13um CMOS

Prior to the introduction of 0.13um CMOS, circuits for 10Gbps serial receivers were implemented in high-speed processes such as SiGe. CMOS processes at channel lengths of 0.13um and smaller have sufficiently fast core devices to process 10Gbps data streams. The architecture and circuit design for a 10Gbps clock and data recovery circuit based upon a half-rate binary phase detector using a delay interpolating VCO will be described; the binary phase detector is the basis of a bang bang phase-locked loop.

The talk will begin with a tutorial overview of the operation and jitter properties of a bang bang phase-locked. It will next delve into the architecture for a half-rate binary phase detector and describe some of the circuit challenges.

Jack Kenney was born in Springfield, MA. He received BS degrees from both Providence College and Columbia University in 1984. His first exposure to analog circuit design was at Motorola Corp. where he developed analog front ends for voiceband telephone applications. Jack received an MSECE and PhD from Carnegie Mellon University in 1988 and 1991 respectively. He was on the faculty of the Department of ECE at Oregon State University from 1992 until 1997 where he achieved the rank of Associate Professor. His other academic posts include Visiting Researcher at the Data Storage Systems Center (DSSC) of the National University of Singapore in Summer 1996, and Visiting Lecturer with the Department of Electrical Engineering at Princeton University in Fall 1999. Jack is now employed by Analog Devices Inc. in Somerset, NJ, where he spent 3 years developing CMOS analog integrated circuits for the ADSL application and is currently designing clock and data recovery circuits for 10Gbps fiber optic channels in 0.13um CMOS.