Design and Optimization Techniques for Large-Scale Asynchronous and Mixed-Timing Systems

Several approaches have been proposed for the synthesis of asynchronous circuits from high-level specification languages. Of particular success in synthesizing large-scale asynchronous systems were syntax-directed compilers, such as Tangram and Balsa. Both compilers have been successfully used in large, real-world applications; however, in practice, these methods suffer from significant performance overheads due to the reliance on straightforward syntax-directed translation.

This talk presents a new optimizing back-end for the Balsa synthesis system. The back-end incorporates a new set of transformations, and an extended component modeling language, called CH, to support them. The transforms fall into two categories: resynthesis and peephole. Peephole optimizations replace existing configurations of components in a template-based fashion by other configurations of components. In contrast, resynthesis optimizations modify and resynthesize a collection of components in a non-template based fashion. All proposed transformations are captured as simple language manipulation procedures in CH.

The new back-end optimizer has been applied on several design examples. Pre-layout simulations indicate system-level performance improvements of up to 54% over the unoptimized implementations. The proposed tool is the first integrated design flow for large-scale systems which incorporates a significant number of powerful optimizing transforms.

The talk will also give a short overview of a complete set of components that interface any combination of asynchronous and synchronous domains. These interface circuits are FIFO's, which have low-latency and support high-throughput.

Bio
Tiberiu Chelcea is a Doctoral student in Computer Science at Columbia University, New York. He has received the B.S. and M.S. Degrees from Politehnica University of Bucharest in 1995, and 1996, respectively. Tiberiu Chelcea's research interests are in the areas of asynchronous CAD, asynchronous design, and mixed-timing interfaces.