Peter Bellows University of Southern California Information Sciences Institute

Rewiring In Orbit: Grooming Programmable Logic for Outer Space

Programmable logic devices such as FPGAs enjoy increasing popularity because they blend simple design, low cost, in-field reprogrammability, and high performance resulting from application-specific circuitry. These capabilities closely match the needs of many space applications, which are typically performance-hungry but do not have the volume to justify the high design cost of fully custom electronics (ASICs). However FPGAs have generally been excluded from space missions because they are particularly susceptible to the harsh environmental constraints of outer space, particularly high-energy particle radiation and power consumption. In this presentation, I describe these environmental constraints and current research activities regarding how to overcome them, such that FPGAs and related technologies can play a prominent role in future space missions. This research includes CAD tools and techniques for device manufacture, design entry, logic redundancy, genetic logic evolution, and system control.

Bio
Mr. Peter Bellows is a researcher for military electronic systems at the University of Southern California, Information Sciences Institute. He has been actively involved in adaptive computing systems research for eight years, creating six generations of FPGA-based systems for signal and image processing and network security. His systems experience ranges from physical design to device drivers, programming models and CAD tools. As a graduate student, he co-authored the JHDL CAD tool suite for FPGA-based systems, which is still in wide use among the FPGA research community. He is a reviewer for the International Conference on Field-Programmable Logic and Applications. He received his B.S. and M.S. Degrees in Electrical and Computer Engineering from Brigham Young University in 1997 and 1999, respectively.